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CY26121
PacketClockTM Spread Spectrum Clock Generator
Features * Integrated phase-locked loop (PLL) * Low jitter, high-accuracy outputs * 3.3V operation * 25-MHz input frequency * 66.66-MHz or 33.33-MHz selectable output frequency (orig, -3,-11,-31) * 33.33-MHz or 25-MHz selectable output frequency (-2,-21) Benefits High-performance PLL tailored for Spread Spectrum application Meets critical timing requirements in complex system designs Enables application compatibility Works with commonly available crystal or driven reference Downspread Spread Spectrum with 30-kHz nominal modulation frequency
Frequency Table for CLKA-D
Part Number CY26121 CY26121-2 CY26121-3 CY26121-11 CY26121-21 CY26121-31 CLKSEL=0 66.66 MHz 33.33 MHz 66.66 MHz 66.66 MHz 33.33 MHz 66.66 MHz CLKSEL=1 33.33 25.00 33.33 33.33 25.00 33.33 Spread% -2.8% -2.8% -1.4% -2.8% -2.8% -1.4% Parallel Crystal Load 6 pF 6 pF 6 pF 15 pF 15 pF 15 pF
Logic Block Diagram
25 MHz XIN XOUT OSC.
VDDL
PLL with Modulation Control
CLKA CLKB CLKC
SSON
OUTPUT MULTIPLEXER AND DIVIDERS
Flash Configuration
CLKD VSSL
CLKSEL
REF VDD AVDD AVSS VSS
Pin Configuration
CY26121 16-pin TSSOP
XIN VDD AVDD CLKSEL AVSS VSSL CLKA CLKB 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XOUT NC REF VSS CLKD VDDL SSON CLKC
Cypress Semiconductor Corporation Document #: 38-07350 Rev. **
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised February 11, 2003
CY26121
Pin Description
Name XIN VDD AVDD CLKSEL CLKSEL AVSS VSSL CLK(A:D) SSON VDDL VSS REF NC XOUT[1] 1 2 3 4 (orig., -11,-3,-31) 4 (-2, -21) 5 6 7,8,9,12 10 11 13 14 15 16 Pin Number Reference input or crystal input 3.3V voltage supply 3.3V analog voltage 0 = 66.66MHz out, 1 = 33.33 MHz out. Weak pull-up. 0 = 33.33MHz out, 1 = 25 MHz out. Weak pull-up. Analog ground CLK ground Clock outputs at VDDL level Spread Spectrum enable pin 0 = SS off; 1 = SS on. Weak pull-up. 3.3V clock voltage supply Ground Reference output at VDD level No Connect Crystal Output Data Retention @ Tj = 125C................................> 10 years Package Power Dissipation...................................... 350 mW Static Discharge Voltage.......................................... > 2000V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Description
Absolute Maximum Conditions
Supply Voltage (VDD, AVDD, VDDL) ...................-0.5 to +7.0V DC Input Voltage...................................... -0.5V to VDD + 0.5 Storage Temperature (Non-condensing) .......................................-55C to +125C Junction Temperature ................................ -40C to +125C
Recommended Operating Conditions
Parameter VDD, AVDD VDDL TA TA CLOAD Fref Supply voltage Supply voltage for CLK (A-D) Ambient temperature (commercial temp. grade) Ambient Temperature (industrial temp grade) Max. output load capacitance Reference frequency 25 Description Min. 3.135 3.135 0 -40 Typ. 3.30 3.30 Max. 3.465 3.465 70 85 15 Unit V V C C pF MHz
Crystal Specification[2]
Parameter CRload CRload ESR Name Crystal load capacitance (original, -2, -3) Crystal load capacitance (-11,-21,-31) Equivalent series resistance Min. Typ 6 15 50 Max. Unit pF pF
Notes: 1. Float XOUT if XIN is externally driven. 2. A fundamental parallel resonant crystal must be used
Document #: 38-07350 Rev. **
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CY26121
DC Electrical Specifications
Parameter IOH IOL IIH IIL VIH VIL CIN[3] RUP[3] IDD Description Output High Current Output Low Current Input High Current Input Low Current Input High Voltage Input Low Voltage Input Capacitance Pull-up resistor on input pins Supply Current Condition VOH = VDD - 0.5, VDD/VDDL=3.3V VOL = 0.5, VDD/VDDL = 3.3V VIH = VDD VIL = 0V CMOS levels CMOS levels Input pins excluding XIN VDD = 3.14 to 3.47V, measured at VIN = 0V AVDD/VDD/VDDL Current. 80 100 42 0.7 0.3 7 150 60 Min. 12 12 Typ. 24 24 5 10 50 Max. Unit mA mA A A VDD VDD pF k mA
AC Electrical Specifications[3]
Parameter DC ER EF tj Description Output Duty Cycle Rising Edge Rate Falling Edge Rate RMS Clock Cycle-to-Cycle Jitter Condition Duty Cycle is defined in Figure 1, 50% of VDD Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 2. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 2. RMS cycle-to-cycle jitter with Spread on. Measured at VDD/2. Min. 45 0.8 0.8 Typ. 50 1.4 1.4 15 40 Max. 55 Unit % V/ns V/ns ps
Voltage and Timing Definitions
t1 t2 VDD 50% of VDD Clock Output 0V
Figure 1. Duty Cycle Definition
t3 t4 V
DD
80% of V DD 20% of V DD 0V
Clock Output
Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4
Notes: 3. Guaranteed by Characterization, not 100% tested.
Document #: 38-07350 Rev. **
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CY26121
Ordering Information
Ordering Code CY26121ZC CY26121ZCT CY26121ZI CY26121ZIT CY26121ZC-2 CY26121ZC-2T CY26121ZI-2 CY26121ZI-2T CY26121ZC-3 CY26121ZC-3T CY26121ZI-3 CY26121ZI-3T CY26121ZC-11 CY26121ZC-11T CY26121ZI-11 CY26121ZI-11T CY26121ZC-21 CY26121ZC-21T CY26121ZI-21 CY26121ZI-21T CY26121ZC-31 CY26121ZC-31T CY26121ZI-31 CY26121ZI-31T Package Type 16-pin TSSOP 16-pin TSSOP - Tape and Reel 16-pin TSSOP 16-pin TSSOP - Tape and Reel 16-pin TSSOP 16-pin TSSOP - Tape and Reel 16-pin TSSOP 16-pin TSSOP - Tape and Reel 16-pin TSSOP 16-pin TSSOP - Tape and Reel 16-pin TSSOP 16-pin TSSOP - Tape and Reel 16-pin TSSOP 16-pin TSSOP - Tape and Reel 16-pin TSSOP 16-pin TSSOP - Tape and Reel 16-pin TSSOP 16-pin TSSOP - Tape and Reel 16-pin TSSOP 16-pin TSSOP - Tape and Reel 16-pin TSSOP 16-pin TSSOP - Tape and Reel 16-pin TSSOP 16-pin TSSOP - Tape and Reel Operating Range Commercial, 0C to 70C Commercial, 0C to 70C Industrial, -40C to 85C Industrial, -40C to 85C Commercial, 0C to 70C Commercial, 0C to 70C Industrial, -40C to 85C Industrial, -40C to 85C Commercial, 0C to 70C Commercial, 0C to 70C Industrial, -40C to 85C Industrial, -40C to 85C Commercial, 0C to 70C Commercial, 0C to 70C Industrial, -40C to 85C Industrial, -40C to 85C Commercial, 0C to 70C Commercial, 0C to 70C Industrial, -40C to 85C Industrial, -40C to 85C Commercial, 0C to 70C Commercial, 0C to 70C Industrial, -40C to 85C Industrial, -40C to 85C
Document #: 38-07350 Rev. **
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CY26121
Package Drawing and Dimensions
16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16
51-85091-**
Inches
Parameter A A1 A2 B C D E e H L a 0.244 0.018 0 Min. - 0.002 0.031 0.007 0.004 0.193 0.169 Nom. - - 0.039 - - 0.197 0.173 0.026 BSC 0.252 0.024 - 0.260 0.030 8 6.20 0.45 0 Max. 0.047 0.006 0.041 0.012 0.008 0.201 0.177 Min. - 0.05 0.80 0.19 0.09 4.90 4.30
Millimeters
Nom. - - 1.00 - - 5.00 4.40 0.65 BSC 6.40 0.60 - 6.60 0.75 8 Max. 1.20 0.15 1.05 0.30 0.20 5.10 4.50
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07350 Rev. **
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(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY26121
Document History Page
Document Title: CY26121 PacketClockTM Spread Spectrum Clock Generator Document Number: 38-07350 REV. ** ECN NO. 121669 Issue Date 02/11/03 Orig. of Change CKN New Data Sheet Description of Change
Document #: 38-07350 Rev. **
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